SidelinkParametersNR-r16
TS 38.331
V18.5.1
2025-03
SidelinkParametersNR-r16 ::= SEQUENCE { rlc-ParametersSidelink-r16 RLC-ParametersSidelink-r16 OPTIONAL, mac-ParametersSidelink-r16 MAC-ParametersSidelink-r16 OPTIONAL, fdd-Add-UE-Sidelink-Capabilities-r16 UE-SidelinkCapabilityAddXDD-Mode-r16 OPTIONAL, tdd-Add-UE-Sidelink-Capabilities-r16 UE-SidelinkCapabilityAddXDD-Mode-r16 OPTIONAL, supportedBandListSidelink-r16 SEQUENCE (SIZE (1..maxBands)) OF BandSidelink-r16 OPTIONAL, ..., [[ relayParameters-r17 RelayParameters-r17 OPTIONAL ]], [[ -- R1 32-x: Use of new P0 parameters for open loop power control p0-OLPC-Sidelink-r17 ENUMERATED {supported} OPTIONAL ]], [[ pdcp-ParametersSidelink-r18 PDCP-ParametersSidelink-r18 OPTIONAL, --R1 41-1-1a: Common SL-PRS processing capability sl-PRS-CommonProcCapabilityPerUE-r18 SEQUENCE { maxNumOfActiveSL-PRS-Resources-r18 SEQUENCE { fr1-r18 ENUMERATED {n1, n2, n4, n6, n8, n12, n16, n24} OPTIONAL, fr2-r18 ENUMERATED {n1, n2, n4, n6, n8, n12, n16, n24, n32, n48, n64, n128} OPTIONAL }, maxNumOfSlotswithActiveSL-PRS-Resources-r18 SEQUENCE { fr1-r18 ENUMERATED {n1, n2, n3, n4, n6, n8} OPTIONAL, fr2-r18 ENUMERATED {n1, n2, n4, n8, n12, n16, n24, n32, n48, n64} OPTIONAL } } OPTIONAL ]] }